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Semiconductor Electronics

Previous year questions with solutions · 2025 – 2026

39Questions
37Papers covered
4.42%Weightage 2026▲ 16.7% vs last year
Year-wise statistics questions · papers · average per paper · weightage
YearQuestionsPapersAvg / paperWeightage
202621191.14.42% ▲ 16.7% vs last year
202518190.953.79%

39 questions · newest paper first · page 1 of 2

Ques. 1JEE Main 2026, 8 April (Evening Shift)

The output Y for the given inputs A and B to the circuit is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 2JEE Main 2026, 6 April (Morning Shift)

The maximum rated power of the LED is 2 mW and it is used in the circuit with input voltage of 5 V as shown in the figure below. The current through resistance RS is 0.5 mA. The minimum value of the resistance of RS, to ensure that the LED is not damaged is k . [figure]

  1. 6
  2. 2
  3. 4
  4. 5
Ques. 3JEE Main 2026, 6 April (Evening Shift)

Refer to the logic circuit given below. For two inputs (A=1, B=1) and (A=0, B=1), output (Y) will be . [figure]

  1. 1, 0 respectively
  2. 0, 1 respectively
  3. 0, 0 respectively
  4. 1, 1 respectively
Ques. 4JEE Main 2026, 5 April (Morning Shift)

For the given logic circuit, which of the following inputs combination will make both LED-1 and LED-2 to glow? [figure]

  1. A = 0, B = 1, C = 1
  2. A = 1, B = 0, C = 0
  3. A = 1, B = 0, C = 1
  4. A = 1, B = 1, C = 0
Ques. 5JEE Main 2026, 5 April (Evening Shift)

In a semiconductor p-n diode, the doping concentrations on p-side and n-side are 1015 atoms/cm3 and 1018 atoms/cm3, respectively. Which one of the following statements is true ?

  1. Widths of depletion region on either side of the interface are equal
  2. The depletion region width is more on p-side compared to that in n-side
  3. The depletion region width is more on n-side compared to that in p-side
  4. No depletion region forms because of unequal doping concentrations on p and n-sides
Ques. 6JEE Main 2026, 4 April (Morning Shift)

Two 4 bits binary numbers, A = 1101 and B = 1010 are given in the inputs of a logic circuit shown in figure below. The output (Y) will be : [figure]

  1. Y = 1101
  2. Y = 0010
  3. Y = 0111
  4. Y = 1000
Ques. 7JEE Main 2026, 4 April (Morning Shift)

Consider a circuit consisting of a capacitor (20 μF), resistor (100 Ω) and two identical diodes as shown in figure. The resistance of diode under forward biasing condition is 10 Ω. The time constant of the circuit is 10-3 s. The value of is . [figure]

  1. 2.2
  2. 2.0
  3. 2.1
  4. 2.4
Ques. 8JEE Main 2026, 4 April (Evening Shift)

Given below are two statements: one is labelled as Assertion (A) and the other is labelled as Reason (R). Choose the correct answer from the options given below :

  1. Both (A) and (R) are true and (R) is the correct explanation of (A)
  2. Both (A) and (R) are true but (R) is NOT the correct explanation of (A)
  3. (A) is true but (R) is false
  4. (A) is false but (R) is true
Ques. 9JEE Main 2026, 4 April (Evening Shift)

A diode has Zener voltage of 10 V and maximum power dissipation of 0.5 W, then the minimum resistance to be used in series with this diode for safety when it is connected to a 25 V power supply is Ω.

Ques. 10JEE Main 2026, 2 April (Morning Shift)

For the given circuit (shown in part (A)) the time dependent input voltage vin(t) and corresponding output vo(t) are shown in part (B) and part (C), respectively. Identify the components that are used in the circuit between points X and Y. [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 11JEE Main 2026, 2 April (Evening Shift)

If X and Y are the inputs, the given circuit works as . [figure]

  1. OR gate
  2. AND gate
  3. NAND gate
  4. NOR gate
Ques. 12JEE Main 2026, 28 January (Morning Shift)

Assuming in forward bias condition there is a voltage drop of 0.7 V across a silicon diode, the current through diode D1 in the circuit is mA. (Assume all diodes in the given circuit are identical) [figure]

  1. 17.6
  2. 18.8
  3. 20.15
  4. 11.7
Ques. 13JEE Main 2026, 28 January (Evening Shift)

Two p-n junction diodes D1 and D2 are connected as shown in figure. A and B are input signals and C is the output. The given circuit will function as a . [figure]

  1. AND Gate
  2. OR Gate
  3. NOR Gate
  4. NAND Gate
Ques. 14JEE Main 2026, 24 January (Morning Shift)

A voltage regulating circuit consisting of Zener diode, having breakdown voltage of 10 V and maximum power dissipation of 0.4 W, is operated at 15 V. The approximate value of protective resistance in this circuit is .

Ques. 15JEE Main 2026, 24 January (Evening Shift)

Identify the correct truth table of the given logic circuit. [figure]

  1. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  2. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  3. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  4. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array
Ques. 16JEE Main 2026, 23 January (Morning Shift)

The following diagram shows a Zener diode as a voltage regulator. The Zener diode is rated at Vz = 5 V and the desired current in load is 5 mA. The unregulated voltage source can supply up to 25 V. Considering the Zener diode can withstand four times the load current, the value of resistor Rs (shown in circuit) should be . [figure]

  1. 100
  2. 10
  3. 1000
  4. 4000
Ques. 17JEE Main 2026, 23 January (Evening Shift)

For the given logic gate circuit, which of the following is the correct truth table? [figure]

  1. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 0 array
  2. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 1 \ 1 & 0 & 0 array
  3. arrayccc n & m & z \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 1 array
  4. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 0 \ 1 & 0 & 0 array
Ques. 18JEE Main 2026, 22 January (Morning Shift)

Find the correct combination of A, B, C and D inputs which can cause the LED to glow. [figure]

  1. 1000
  2. 0011
  3. 0100
  4. 1101
Ques. 19JEE Main 2026, 22 January (Evening Shift)

The correct truth table for the given input data of the following logic gate is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 20JEE Main 2026, 21 January (Morning Shift)

The given circuit works as : [figure]

  1. NOR gate
  2. OR gate
  3. AND gate
  4. NAND gate
Ques. 21JEE Main 2026, 21 January (Evening Shift)

The charge stored by the capacitor C in the given circuit in the steady state is . [figure]

  1. 7.5
  2. 5
  3. 10
  4. 12.5
Ques. 22JEE Main 2025, 8 April (Evening Shift)

The output voltage in the following circuit is (Consider ideal diode case) [figure]

  1. 0 V
  2. +5 V
  3. −5 V
  4. 10 V
Ques. 23JEE Main 2025, 7 April (Morning Shift)

In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V) [figure]

  1. 60 mA
  2. 80 mA
  3. 10 mA
  4. 24 mA
Ques. 24JEE Main 2025, 7 April (Evening Shift)

Consider the following logic circuit. [figure] The output is Y = 0 when :

  1. A = 1 and B = 0
  2. A = 0 and B = 0
  3. A = 1 and B = 1
  4. A = 0 and B = 1
Ques. 25JEE Main 2025, 4 April (Morning Shift)

The Boolean expression Y = A BC + A C can be realised with which of the following gate configurations. Choose the correct answer from the options given below:

  1. B, C Only
  2. A, B, C Only
  3. A, B Only
  4. A, C Only
Ques. 26JEE Main 2025, 4 April (Evening Shift)

Consider an n-type semiconductor in which ne and nh are number of electrons and holes, respectively. Choose the correct answer from the options given below :

  1. (A), (B), (E) only
  2. (A), (C), (E) only
  3. (A), (B), (C) only
  4. (A), (C), (D) only
Ques. 27JEE Main 2025, 3 April (Morning Shift)

Choose the correct logic circuit for the given truth table having inputs A and B. [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 28JEE Main 2025, 3 April (Evening Shift)

The truth table corresponding to the circuit given below is: [figure]

  1. arrayccc A & B & C \ 0 & 0 & 0 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 1 array
  2. arrayccc A & B & C \ 0 & 0 & 1 \ 1 & 0 & 0 \ 0 & 1 & 0 \ 1 & 1 & 0 array
  3. arrayccc A & B & C \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 0 \ 1 & 1 & 0 array
  4. arrayccc A & B & C \ 0 & 0 & 0 \ 1 & 0 & 0 \ 0 & 1 & 0 \ 1 & 1 & 1 array
Ques. 29JEE Main 2025, 2 April (Morning Shift)

A zener diode with 5 V zener voltage is used to regulate an unregulated dc voltage input of 25 V. For a 400 resistor connected in series, the zener current is found to be 4 times load current. The load current (IL) and load resistance (RL) are :

  1. IL = 0.02 mA; RL = 250
  2. IL = 10 A; RL = 0.5
  3. IL = 10 mA; RL = 500
  4. IL = 20 mA; RL = 250
Ques. 30JEE Main 2025, 2 April (Evening Shift)

In the digital circuit shown in the figure, for the given inputs the P and Q values are : [figure]

  1. P = 0, Q = 1
  2. P = 1, Q = 0
  3. P = 0, Q = 0
  4. P = 1, Q = 1