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Semiconductor Electronics

JEE Main 2026 (Online) 28th January Evening ShiftMCQMedium📈 Topic in 53% papers+4−1
Ques. 1JEE Main 2026, 28 January (Evening Shift)

Two p-n junction diodes D1 and D2 are connected as shown in figure. A and B are input signals and C is the output. The given circuit will function as a . [figure]

  1. AND Gate
  2. OR Gate
  3. NOR Gate
  4. NAND Gate

Answer

(1) AND Gate

Solution

The p-sides of both diodes are joined to +5 V through R and their n-sides go to the inputs A and B.

If an input is 0 (low), the diode connected to it is forward biased and conducts; the output C is pulled down to 0.

Only when A = 1 and B = 1 (both at 5 V), neither diode conducts, no current flows through R and C = 5 V, i.e. C = 1.

Truth table: (A, B) = (0, 0) C = 0; (0, 1) C = 0; (1, 0) C = 0; (1, 1) C = 1

C = A B, the circuit works as an AND gate.

Answer: (1)

Keep practising — Semiconductor Electronics

Ques. 2JEE Main 2026, 24 January (Morning Shift)

A voltage regulating circuit consisting of Zener diode, having breakdown voltage of 10 V and maximum power dissipation of 0.4 W, is operated at 15 V. The approximate value of protective resistance in this circuit is .

Ques. 3JEE Main 2026, 24 January (Evening Shift)

Identify the correct truth table of the given logic circuit. [figure]

  1. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  2. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  3. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  4. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array
Ques. 4JEE Main 2026, 23 January (Morning Shift)

The following diagram shows a Zener diode as a voltage regulator. The Zener diode is rated at Vz = 5 V and the desired current in load is 5 mA. The unregulated voltage source can supply up to 25 V. Considering the Zener diode can withstand four times the load current, the value of resistor Rs (shown in circuit) should be . [figure]

  1. 100
  2. 10
  3. 1000
  4. 4000
Ques. 5JEE Main 2026, 23 January (Evening Shift)

For the given logic gate circuit, which of the following is the correct truth table? [figure]

  1. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 0 array
  2. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 1 \ 1 & 0 & 0 array
  3. arrayccc n & m & z \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 1 array
  4. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 0 \ 1 & 0 & 0 array
Ques. 6JEE Main 2026, 22 January (Morning Shift)

Find the correct combination of A, B, C and D inputs which can cause the LED to glow. [figure]

  1. 1000
  2. 0011
  3. 0100
  4. 1101
Ques. 7JEE Main 2026, 22 January (Evening Shift)

The correct truth table for the given input data of the following logic gate is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 8JEE Main 2026, 21 January (Morning Shift)

The given circuit works as : [figure]

  1. NOR gate
  2. OR gate
  3. AND gate
  4. NAND gate
Ques. 9JEE Main 2026, 21 January (Evening Shift)

The charge stored by the capacitor C in the given circuit in the steady state is . [figure]

  1. 7.5
  2. 5
  3. 10
  4. 12.5
Ques. 10JEE Main 2025, 8 April (Evening Shift)

The output voltage in the following circuit is (Consider ideal diode case) [figure]

  1. 0 V
  2. +5 V
  3. −5 V
  4. 10 V
Ques. 11JEE Main 2025, 7 April (Morning Shift)

In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V) [figure]

  1. 60 mA
  2. 80 mA
  3. 10 mA
  4. 24 mA

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