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Semiconductor Electronics

JEE Main 2026 (Online) 23rd January Evening ShiftMCQEasy📈 Topic in 55% papers+4−1
Ques. 1JEE Main 2026, 23 January (Evening Shift)

For the given logic gate circuit, which of the following is the correct truth table? [figure]

  1. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 0 array
  2. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 1 \ 1 & 0 & 0 array
  3. arrayccc n & m & z \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 1 array
  4. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 0 \ 1 & 0 & 0 array

Answer

(1) arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 0 array

Solution

Output of the OR gate: n + m

The NAND gate gets n and n + m:

z = n (n + m) = n n + n m = n + n m = n ( n + n m = n)

z = 1 when n = 0 and z = 0 when n = 1, whatever m is:

(0, 0) → 1, (0, 1) → 1, (1, 1) → 0, (1, 0) → 0

Answer: (1)

Keep practising — Semiconductor Electronics

Ques. 2JEE Main 2026, 22 January (Morning Shift)

Find the correct combination of A, B, C and D inputs which can cause the LED to glow. [figure]

  1. 1000
  2. 0011
  3. 0100
  4. 1101
Ques. 3JEE Main 2026, 22 January (Evening Shift)

The correct truth table for the given input data of the following logic gate is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 4JEE Main 2026, 21 January (Morning Shift)

The given circuit works as : [figure]

  1. NOR gate
  2. OR gate
  3. AND gate
  4. NAND gate
Ques. 5JEE Main 2026, 21 January (Evening Shift)

The charge stored by the capacitor C in the given circuit in the steady state is . [figure]

  1. 7.5
  2. 5
  3. 10
  4. 12.5
Ques. 6JEE Main 2025, 8 April (Evening Shift)

The output voltage in the following circuit is (Consider ideal diode case) [figure]

  1. 0 V
  2. +5 V
  3. −5 V
  4. 10 V
Ques. 7JEE Main 2025, 7 April (Morning Shift)

In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V) [figure]

  1. 60 mA
  2. 80 mA
  3. 10 mA
  4. 24 mA
Ques. 8JEE Main 2025, 7 April (Evening Shift)

Consider the following logic circuit. [figure] The output is Y = 0 when :

  1. A = 1 and B = 0
  2. A = 0 and B = 0
  3. A = 1 and B = 1
  4. A = 0 and B = 1
Ques. 9JEE Main 2025, 4 April (Morning Shift)

The Boolean expression Y = A BC + A C can be realised with which of the following gate configurations. Choose the correct answer from the options given below:

  1. B, C Only
  2. A, B, C Only
  3. A, B Only
  4. A, C Only
Ques. 10JEE Main 2025, 4 April (Evening Shift)

Consider an n-type semiconductor in which ne and nh are number of electrons and holes, respectively. Choose the correct answer from the options given below :

  1. (A), (B), (E) only
  2. (A), (C), (E) only
  3. (A), (B), (C) only
  4. (A), (C), (D) only
Ques. 11JEE Main 2025, 3 April (Morning Shift)

Choose the correct logic circuit for the given truth table having inputs A and B. [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]

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